The present invention relates to a semiconductor integrated circuit that prevents a malfunction caused by noise on power supply nets and is suitable to cost reduction, and in particular, to a CMOS processor.
Now, researches and developments of gigahertz CMOS processors are vigorously performed. In order to enable operation in gigahertz, noise-proof engineering becomes important with a high-speed circuit technology. It is because the noise on the power supply nets generates delay deterioration and a malfunction of a circuit and it becomes an obstruction of acceleration. The noise on power supply nets in an LSI chip is roughly divided into: (1) RF noise by circuit operation; and (2) direct current drop by a power supply resistance, and the item (1) is dominant in particular.
As a general measure of RF noise reduction, there is a method of mounting bypass capacitors or condensers in an LSI chip. This is a method of connecting bypass condensers to respective places of power supply nets so that a malfunction may not occur to the worst noise in the LSI chip.
FIG. 15 shows a conventional semiconductor integrated circuit on which bypass condensers are mounted. Power supply nets inside a chip are arranged in a mesh-like shape in the XY directions. The bypass condensers are arranged in an area just under the power supply nets inside the chip in the Y direction, and areas, which are vacant after spreading gates all over, as much as possible. A bypass condenser is typically formed with a capacity between gate channels of an MOS transistor. In a PMOS transistor, VSS is connected to a gate, and a drain and a source are connected to VDD. In an NMOS transistor, VDD is connected to a gate, and VSS is connected to a drain and a source. Moreover, a necessary amount of condensers is decided in consideration of the switching current of MOS transistors in an entire chip. In a certain processor chip that has the power dissipation of 100 W with the chip size of 17 mm square, bypass condensers occupy 20% of chip size.
In future LSI chips, further acceleration and high integration progress will be advanced, and hence the increase of the noise on power supply nets can be predicted. Thus, the impedance of power supply nets becomes high by the acceleration, and power dissipation increases by high integration, and hence the noise on the power supply nets increases.
On the other hand, as a preventive measure against a malfunction caused by the noise on power supply nets, a method of detecting the noise and performing interruption is known. As a conventional method of the noise detection and interruption processing, for example, a method described in JP-A-9-73400 is known. The external noise that invades into the power supply nets of an I/O circuit section arranged around a semiconductor integrated circuit is detected, and a malfunction of internal circuits is prevented by the interruption.
Furthermore, as a noise detecting circuit, for example, a circuit described in U.S. Pat. No. 6,191,647 is known. This circuit has the structure of receiving power supply from a power supply line other than a power supply line set as an object of noise observation to avoid that noise on the power supply nets influences the observation of noise itself.